Phase-error correction by single-phase phase-locked loops based on transfer delay

Comparative studies of different single-phase phase-locked loops (PLL) algorithms have been made. They show that the PLL based on sample delay (dPLL), presents the lowest computational load and is as robust as the three-phase synchronous reference frame PLL dqPLL by input signal amplitude and phase variations. Its weakness appears when the input signal frequency differs from its rated frequency: It depicts a steady error on the calculated signal phase-angle. After a brief review of the dqPLL which constitutes debase structure of the dPLL, the following work will present three methods that improve the phase detection accuracy of dPLL. It is shown that the modifications brought in the original structure do not influence the robustness and stability of the algorithm but reduce the phase angle offset error by input signal frequency variation. This is corroborated by tests including not only the fundamental input voltage disturbance like amplitude, phase and frequency variation but also harmonic voltage distortion.