Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances

Reference : Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances


	Document type :	Scientific congresses, symposiums and conference proceedings : Paper published in a book
	Discipline(s) :	Engineering, computing & technology : Electrical & electronics engineering
	To cite this reference:	http://hdl.handle.net/10993/20676

Title :	Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances
Language :	English
Author, co-author :	Klaes, D. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Moers, J. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Tönnesmann, A. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Grimm, M. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Wickenhäuser, S. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Vescan, L. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Marso, Michel [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Kordoš, P. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
	Lüth, H. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Publication date :	1998
Main document title :	Proceedings of the 28th European Solid State Devices Research Conference, Bordeaux, France
Pages :	568-571
Peer reviewed :	No
Event name :	28th European Solid State Devices Research Conference, Bordeaux, France
Event date :	1998
Permalink :	http://hdl.handle.net/10993/20676

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