Gate oxide; Vertical field-e ffect transistor; Low temperature oxidation
Abstract :
[en] In this work, we present an approach towards improving a vertical eld-e ect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant di ffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.
Disciplines :
Electrical & electronics engineering
Identifiers :
UNILU:UL-ARTICLE-2009-389
Author, co-author :
Goryll, M.; Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany
Moers, J.; Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany
Trellenkamp, S.; Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany
Vescan, L.; Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany
Marso, Michel ; Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany
Kordos, P.; Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany
Luth, H.; Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany
Language :
English
Title :
Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors,
Publication date :
2003
Journal title :
Physica E: Low-Dimensional Systems and Nanostructures