Reference : An Evaluation of the Multi-Platform Efficiency of Lightweight Cryptographic Permutations

	Document type :	Scientific congresses, symposiums and conference proceedings : Paper published in a book
	Discipline(s) :	Engineering, computing & technology : Computer science
	Focus Areas :	Security, Reliability and Trust
	To cite this reference:	http://hdl.handle.net/10993/52367

Title :	An Evaluation of the Multi-Platform Efficiency of Lightweight Cryptographic Permutations
Language :	English
Author, co-author :	Cardoso Dos Santos, Luan [University of Luxembourg > Faculty of Science, Technology and Medicine (FSTM) > Department of Computer Science (DCS) >]
	Groszschädl, Johann [University of Luxembourg > Faculty of Science, Technology and Medicine (FSTM) > Department of Computer Science (DCS) >]
Publication date :	Nov-2021
Main document title :	Innovative Security Solutions for Information Technology and Communications 14th International Conference, SECITC 2021, Virtual Event, November 25-26, 2021, Revised Selected Papers
Editor :	Ryan, Peter Y A
	Toma, Cristian
Publisher :	Springer Verlag
Collection and collection volume :	vol. 13195 of Lecture Notes in Computer Science
Pages :	70-85
Peer reviewed :	Yes
ISBN :	978-3-031-17509-1
Event name :	14th International Conference on Security for Information Technology and Communications (SecITC 2021)
Event date :	from 25-11-2021 to 26-11-2021
Event place (city) :	Bucharest
Event country :	Romania
Keywords :	[en] Lightweight Cryptography ; Permutation-Based Cryptography ; Authenticated Encryption ; Assembly Optimization ; Performance Evaluation
Abstract :	[en] Permutation-based symmetric cryptography has become increasingly popular over the past ten years, especially in the lightweight domain. More than half of the 32 second-round candidates of NIST's lightweight cryptography standardization project are permutation-based designs or can be instantiated with a permutation. The performance of a permutation-based construction depends, among other aspects, on the rate (i.e. the number of bytes processed per call of the permutation function) and the execution time of the permutation. In this paper we analyze the execution time and code size of assembler implementations of the permutation of Ascon, Gimli, Schwaemm, and Xoodyak on an 8-bit AVR and a 32-bit ARM Cortex-M3 microcontroller. Our aim is to ascertain how well these four permutations perform on microcontrollers with very different architectural and micro-architectural characteristics such as the available register capacity or the latency of multi-bit shifts and rotations. We also determine the impact of flash wait states on the execution time of the permutations on Cortex-M3 development boards with 0, 2, and 4 wait states. Our results show that the throughput (in terms of permutation time divided by rate when the capacity is fixed to 256 bits) of the permutation of Ascon, Schwaemm, and Xoodyak is similar on ARM Cortex-M3 and lies in the range of 41.1 to 48.6 cycles per rate-byte. However, on an 8-bit AVR ATmega128, the permutation of Schwaemm outperforms its counterparts of Ascon and Xoodyak by a factor of 1.20 and 1.59, respectively.
Permalink :	http://hdl.handle.net/10993/52367
DOI :	10.1007/978-3-031-17510-7_6
Other URL :	http://link.springer.com/chapter/10.1007/978-3-031-17510-7_6
Commentary :	A preliminary version of this paper was presented at the 4th NIST Workshop on Lightweight Cryptography (LWC 2020).

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