Reference : Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits on the...
Scientific congresses, symposiums and conference proceedings : Unpublished conference
Engineering, computing & technology : Computer science
Exploiting Transistor-Level Reconfiguration to Optimize Combinational Circuits on the Example of a Conditional Sum Adder
Raitza, Michael []
Kumar, Akash []
Volp, Marcus mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Walter, Dennis []
Trommer, Jens []
Mikolajick, Thomas []
Weber, Walter M. []
Design, Automation and Test in Europe (DATE 2017)
27 - 31 March 2017
[en] reconfigurable transistor ; silicon nanowire transistor ; RFET ; TIGFET ; FET ; conditional sum adder ; conditional carry adder ; reconfigurable circuit ; reconfiguration
[en] Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free technology. However, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so far. In this paper, we present first steps to a new compact and efficient design of combinational circuits by employing transistor-level reconfiguration. We contribute new basic gates realized with silicon nanowires, such as 2/3-XOR and MUX gates. Exemplifying our approach with 4-bit, 8-bit and 16-bit conditional carry adders, we were able to reduce the number of transistors to almost one half. With our current case study we show that SiNW technology can reduce the required chip area by 16 %, despite larger size of the individual transistor, and improve circuit speed by 26 %.
Technische Universit├Ąt Dresden, Dresden, Germany; SnT - University of Luxembourg, Luxembourg; Namlab gGmbH Dresden, Germany

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