Article (Scientific journals)
Selectively Grown Vertical Si MOS Transistor with Reduced Overlap Capacitances
Klaes, D.; Moers, J.; Tönnesmann, A. et al.
1998In Thin Solid Films, 336 (1998), p. 306-308
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Keywords :
Low pressure chemical vapour deposition; Selective epitaxial growth; MOS transistor; Miller capacitance
Abstract :
[en] Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving short channel lengths and high integration densities while still using optical lithography to define lateral dimensions. Compared to other vertical concepts, this layout has reduced gate to source/drain overlap capacitances which is necessary for high speed applications. The use of SEG instead of blanket epitaxy avoids the deterioration of the Si/SiO2 interface due to reactive ion etching (RIE) and reduces punch-through due to facet growth. First non-optimized p-channel MOSFETs with a 12-nm gate oxide show a transconductance of 90 mS/mm. The cut-off frequencies of this device turned out to be f T = 2.3 GHz and f max = 1.1 GHz.
Disciplines :
Electrical & electronics engineering
Identifiers :
UNILU:UL-ARTICLE-2009-370
Author, co-author :
Klaes, D.;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
Moers, J.;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
Tönnesmann, A.;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
Wickenhäuser, S.;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
Vescan, L.;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
Marso, Michel ;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
Grabolla, T.;  Institute for Semiconductor Physics, Walter-Korsing-Strasse 2, 15230 Frankfurt Oder, Germany
Grimm, M.;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
Lüth, H.;  Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
External co-authors :
yes
Language :
English
Title :
Selectively Grown Vertical Si MOS Transistor with Reduced Overlap Capacitances
Publication date :
1998
Journal title :
Thin Solid Films
ISSN :
0040-6090
Publisher :
Elsevier Science
Volume :
336
Issue :
1998
Pages :
306-308
Peer reviewed :
Peer Reviewed verified by ORBi
Available on ORBilu :
since 29 March 2015

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