[BCO04] E. Brier, C. Clavier, and F. Olivier. Correlation power analysis with a leakage model. In Cryptographic Hardware and Embedded Systems (CHES), LNCS 3156, pages 16–29. Springer-Verlag, 2004. https://doi.org/10.1007/978-3-540-28632-5_2.
[BDLU17] A. Biryukov, D. Dinu, Y. Le Corre, and A. Udovenko. Optimal first-order Boolean masking for embedded IoT devices. In Smart Card Research and Advanced Applications (CARDIS), LNCS 10728, pages 22–41. Springer-Verlag, 2017. https://doi.org/10.1007/978-3-319-75208-2_2.
[BDP+ 12] G. Bertoni, J. Daemen, M. Peeters, G. Van Assche, and R. Van Keer. Keccak implementation overview. Technical report, 2012. https://keccak.team/files/Keccak-implementation-3.2.pdf.
[BWG+ 22] A. Beckers, L. Wouters, B. Gierlichs, B. Preneel, and I. Verbauwhede. Provable secure software masking in the real-world. In Constructive Side-Channel Analysis and Secure Design (COSADE), LNCS 13211, pages 215–235. Springer-Verlag, 2022. https://doi.org/10.1007/978-3-030-99766-3_10.
[CB23] S. Cui and J. Balasch. Efficient software masking of AES through instruction set extensions. In Design, Automation & Test in Europe (DATE), pages 1–6, 2023. https://doi.org/10.23919/DATE56975.2023.10137150.
[CBCH23] L. Casalino, N. Belleville, D. Couroussé, and K. Heydemann. A tale of resilience: On the practical security of masked software implementations. IEEE Access, 11:84651–84669, 2023. https://doi.org/10.1109/ACCESS.2023.3298436.
[CKK+ 22] P. Choi, W. Kong, J.-H. Kim, M.-K. Lee, and D.K. Kim. Architectural supports for block ciphers in a RISC CPU core by instruction overloading. IEEE Transactions on Computers, 71(11):2844–2857, 2022. https://doi. org/10.1109/TC.2021.3050515.
[DGH19] E. De Mulder, S. Gummalla, and M. Hutter. Protecting RISC-V against side-channel attacks. In Design Automation Conference (DAC), pages 45:1–45:4, 2019. https://doi.org/10.1145/3316781.3323485.
[EFLL20] M. Escouteloup, J.J.A. Fournier, J.-L. Lanet, and R. Lashermes. Recommendations for a radically secure ISA. In Computer Architecture Research with RISC-V (CARRV), 2020. https://carrv.github.io/2020.
[GD23] J. Gaspoz and S. Dhooghe. Threshold implementations in software: Microarchitectural leakages in algorithms. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2023(2):155–179, 2023. https://doi.org/10.46586/tches.v2023.i2.155-179.
[GGM+ 21] S. Gao, J. Großschädl, B. Marshall, D. Page, T.H. Pham, and F. Regaz-zoni. An instruction set extension to support software-based masking. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2021(4):283–325, 2021. https://doi.org/10.46586/tches.v2021. i4.283-325.
[GHP+ 21] B. Gigerl, V. Hadzic, R. Primas, S. Mangard, and R. Bloem. Coco: Co-design and co-verification of masked software implementations on CPUs. In USENIX Security Symposium, pages 1469–1468, 2021. https://www.usenix. org/conference/usenixsecurity21/presentation/gigerl.
[GJJR11] G. Goodwill, B. Jun, J. Jaffe, and Rohatgi. A testing methodology for side-channel resistance validation. NIST Non-Invasive Attack Testing Workshop, 2011. https://csrc.nist.gov/csrc/media/events/non-invasive-attack-testing-workshop/documents/08_goodwill.pdf.
[GJM+ 17] H. Gross, M. Jelinek, S. Mangard, T. Unterluggauer, and M. Werner. Con-cealing secrets in embedded processors designs. In Smart Card Research and Advanced Applications (CARDIS), LNCS 10146, pages 89–104. Springer-Verlag, 2017. https://doi.org/10.1007/978-3-319-54669-8_6.
[GMPO19] S. Gao, B. Marshall, D. Page, and E. Oswald. Share slicing: friend or foe? IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2020(1):152–174, 2019. https://doi.org/10.13154/tches.v2020. i1.152-174.
[GMPP20] S. Gao, B. Marshall, D. Page, and T.H. Pham. FENL: an ISE to mitigate analogue micro-architectural leakage. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2020(2):73–98, 2020. https://doi.org/10.13154/tches.v2020.i2.73-98.
[GYH18] Q. Ge, Y. Yarom, and G. Heiser. No security without time protection: we need a new hardware-software contract. In Asia-Pacific Workshop on Systems (APSys), pages 1:1–1:9, 2018. https://doi.org/10.1145/3265723.3265724.
[HB21] V. Hadzic and R. Bloem. COCOALMA: A versatile masking verifier. In Formal Methods in Computer Aided Design (FMCAD), pages 1–10. IEEE, 2021. https://doi.org/10.34727/2021/isbn.978-3-85448-046-4_9.
[KJJ99] P.C. Kocher, J. Jaffe, and B. Jun. Differential power analysis. In Advances in Cryptology (CRYPTO), LNCS 1666, pages 388–397. Springer-Verlag, 1999. https://doi.org/10.1007/3-540-48405-1_25.
[KS20] P. Kiaei and P. Schaumont. Domain-oriented masked instruction set architecture for RISC-V. Cryptology ePrint Archive, Report 2020/465, 2020. https://eprint.iacr.org/2020/465.
[LHP20] T. Li, B. Hopkins, and S. Parameswaran. SIMF: Single-instruction multiple-flush mechanism for processor temporal isolation. CoRR, abs/2011.10249, 2020. https://arxiv.org/abs/2011.10249.
[LT23] F. Lozachmeur and A. Tisserand. A RISC-V instruction set extension for flex-ible hardware/software protection of cryptosystems masked at high orders. In IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2023.
[MOP07] S. Mangard, E. Oswald, and T. Popp. Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer, 2007. https://doi.org/10.1007/978-0-387-38162-6.
[MP21] B. Marshall and D. Page. SME: Scalable masking extensions. Cryptology ePrint Archive, Report 2021/1416, 2021. https://eprint.iacr.org/2021/1416.
[MPW22] B. Marshall, D. Page, and J. Webb. MIRACLE: MIcRo-ArChitectural Leakage Evaluation. IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2022(1):175–220, 2022. https://doi.org/10.46586/tches. v2022.i1.175-220.
[MR04] S. Micali and L. Reyzin. Physically observable cryptography. In Theory of Cryptography (TCC), LNCS 2951, pages 278–296. Springer-Verlag, 2004. https://doi.org/10.1007/978-3-540-24638-1_16.
[PV17] K. Papagiannopoulos and N. Veshchikov. Mind the gap: Towards secure 1st-order masking in software. In Constructive Side-Channel Analysis and Secure Design (COSADE), LNCS 10348, pages 282–297. Springer-Verlag, 2017. https://doi.org/10.1007/978-3-319-64647-3_17.
[RV:19a] The RISC-V instruction set manual. Technical Report Volume I: User-Level ISA (version 20190608-Base-Ratified), 2019. http://riscv.org/specifications.
[RV:19b] The RISC-V instruction set manual. Technical Report Volume II: Privileged Architecture (version 20190608-Priv-MSU-Ratified), 2019. http://riscv. org/specifications.
[SCS+ 21] M.A. Shelton, L. Chmielewski, N. Samwel, M. Wagner, L. Batina, and Y. Yarom. Rosita++: Automatic higher-order leakage elimination from cryptographic code. In Computer and Communications Security (CCS), pages 685–699, 2021. https://doi.org/10.1145/3460120.3485380.
[SS22] K. Stangherlin and M. Sachdev. Design and implementation of a secure RISC-V microprocessor. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 30(11):1705–1715, 2022. https://doi.org/10.1109/TVLSI.2022. 3203307.
[SSB+ 21] M.A. Shelton, N. Samwel, L. Batina, F. Regazzoni, M. Wagner, and Y. Yarom. Rosita: Towards automatic elimination of power-analysis leakage in ciphers. In Network and Distributed System Security Symposium (NDSS), 2021. https://doi.org/10.14722/ndss.2021.23137.
[TKS10] S. Tillich, M. Kirschbaum, and A. Szekely. SCA-resistant embedded proces-sors: The next generation. In Annual Computer Security Applications Conference (ACSAC), pages 211–220, 2010. https://doi.org/10.1145/1920261. 1920293.
[Wat16] A. Waterman. Design of the RISC-V Instruction Set Architecture. PhD thesis, University of California at Berkeley, 2016. https://people.eecs.berkeley. edu/~krste/papers/EECS-2016-1.pdf.
[WMSN19] R.N.M. Watson, S.W. Moore, P. Sewell, and P.G. Neumann. An introduction to CHERI. Technical Report UCAM-CL-TR-941, University of Cambridge, 2019. https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf.
[WSG+ 20] N. Wistoff, M. Schneider, F.K. Gürkaynak, L. Benini, and G. Heiser. Prevention of microarchitectural covert channels on an open-source 64-bit RISC-V core. In Computer Architecture Research with RISC-V (CARRV), 2020. https://carrv.github.io/2020.
