[en] Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.
Disciplines :
Ingénierie électrique & électronique
Auteur, co-auteur :
Asif, Muhammad
KHAN, Wali Ullah ; University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom
Afzal, H. M. Rehman
Nebhen, Jamel
Ullah, Inam
Rehman, Ateeq Ur
K. A. Kaabar, Mohammed
Co-auteurs externes :
yes
Langue du document :
Anglais
Titre :
Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks
Titre traduit :
[en] Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks
Date de publication/diffusion :
septembre 2021
Titre du périodique :
Wireless Communications and Mobile Computing
ISSN :
1530-8669
eISSN :
1530-8677
Maison d'édition :
John Wiley & Sons, Hoboken, Etats-Unis - New Jersey
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