Reference : An Optimization Approach for an RLL-Constrained LDPC Coded Recording System Using De... |
Scientific journals : Article | |||
Engineering, computing & technology : Electrical & electronics engineering | |||
Computational Sciences | |||
http://hdl.handle.net/10993/50867 | |||
An Optimization Approach for an RLL-Constrained LDPC Coded Recording System Using Deliberate Flipping | |
English | |
Chou, Hung-Pu ![]() | |
Sham, Chiu-Wing ![]() | |
Hong-fu, Chou [] | |
Jun-2018 | |
IEEE Communications Letters | |
Institute of Electrical and Electronics Engineers | |
Yes | |
International | |
1089-7798 | |
New York | |
NY | |
[en] Parity check codes ; iterative decoding ; partial response channels ; error correction codes | |
[en] For a recording system that has a run-length-limited (RLL) constraint, this approach imposes the hard error by flipping bits before recording. A high error coding rate limits the correcting capability of the RLL bit error. Since iterative decoding does not include the estimation technique, it has the
potential capability of solving the hard error bits within several 7 iterations compared to an LDPC coded system. In this letter, we implement density evolution and the differential evolution approach to provide a performance evaluation of unequal error protection LDPC code to investigate the optimal LDPC code distribution for an RLL flipped system. | |
http://hdl.handle.net/10993/50867 |
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