Reference : Design Optimization for Low-Complexity FPGA Implementation of Symbol-Level Multiuser ...
Scientific journals : Article
Engineering, computing & technology : Electrical & electronics engineering
Security, Reliability and Trust
http://hdl.handle.net/10993/46578
Design Optimization for Low-Complexity FPGA Implementation of Symbol-Level Multiuser Precoding
English
Haqiqatnejad, Alireza mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom >]
Krivochiza, Jevgenij mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom >]
Merlano Duncan, Juan Carlos mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom >]
Chatzinotas, Symeon mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom >]
Ottersten, Björn mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
16-Feb-2021
IEEE Access
IEEE
9
30698-30711
Yes (verified by ORBilu)
International
2169-3536
2169-3536
United States
[en] Constructive interference ; Convex optimization ; Downlink multiuser multiple-input single-output (MISO) system ; Field-programmable gate array (FPGA) ; Hardware description language (HDL) ; Non-negative least squares (NNLS) problem ; Symbol-level precoding
[en] This paper proposes and validates a low-complexity FPGA design for symbol-level precoding (SLP) in multiuser multiple-input single-output (MISO) downlink communication systems. In the optimal case, the symbol-level precoded transmit signal is obtained as the solution to an optimization problem tailored for a given set of users’ data symbols. This symbol-by-symbol design, however, imposes excessive computational complexity on the system. To alleviate this issue, we aim to reduce the per-symbol complexity of the SLP scheme by developing an approximate yet computationally-efficient closed-form solution. The proposed solution allows us to achieve a high symbol throughput in real-time implementations. To develop the FPGA design, we express the proposed solution in an algorithmic way and translate it to hardware description language (HDL). We then optimize the processing to accelerate the performance and generate the corresponding intellectual property (IP) core. We provide the synthesis report for the generated IP core, including performance and resource utilization estimates and interface descriptions. To validate our design, we simulate an uncoded transmission over a downlink multiuser channel using the LabVIEW software, where the SLP IP core is implemented as a clock-driven logic (CDL) unit. Our simulation results show that a throughput of 100 Mega symbols per second per user can be achieved via the proposed SLP design. We further use the MATLAB software to produce numerical results for the conventional zero-forcing (ZF) and the optimal SLP techniques as benchmarks for comparison. Thereby, it is shown that the proposed FPGA implementation of SLP offers an improvement of up to 50 percent in power efficiency compared to the ZF precoding. Remarkably, it enjoys the same per-symbol complexity order as that of the ZF technique. We also evaluate the loss of the real-time SLP design, introduced by the algebraic approximations and arithmetic inaccuracies, with respect to the optimal scheme.
Interdisciplinary Centre for Security, Reliability and Trust (SnT) > SIGCOM
Fonds National de la Recherche - FnR
Researchers ; Professionals ; Students
http://hdl.handle.net/10993/46578
10.1109/ACCESS.2021.3059936
https://ieeexplore.ieee.org/document/9355138
FnR ; FNR11332341 > Farbod Kayhan > ESSTIMS > Enhanced Signal Space Optimization For Satellite Communication Systems > 01/02/2017 > 31/01/2020 > 2016

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