Article (Scientific journals)
Design Optimization for Low-Complexity FPGA Implementation of Symbol-Level Multiuser Precoding
Haqiqatnejad, Alireza; Krivochiza, Jevgenij; Merlano Duncan, Juan Carlos et al.
2021In IEEE Access, 9, p. 30698-30711
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Keywords :
Constructive interference; Convex optimization; Downlink multiuser multiple-input single-output (MISO) system; Field-programmable gate array (FPGA); Hardware description language (HDL); Non-negative least squares (NNLS) problem; Symbol-level precoding
Abstract :
[en] This paper proposes and validates a low-complexity FPGA design for symbol-level precoding (SLP) in multiuser multiple-input single-output (MISO) downlink communication systems. In the optimal case, the symbol-level precoded transmit signal is obtained as the solution to an optimization problem tailored for a given set of users’ data symbols. This symbol-by-symbol design, however, imposes excessive computational complexity on the system. To alleviate this issue, we aim to reduce the per-symbol complexity of the SLP scheme by developing an approximate yet computationally-efficient closed-form solution. The proposed solution allows us to achieve a high symbol throughput in real-time implementations. To develop the FPGA design, we express the proposed solution in an algorithmic way and translate it to hardware description language (HDL). We then optimize the processing to accelerate the performance and generate the corresponding intellectual property (IP) core. We provide the synthesis report for the generated IP core, including performance and resource utilization estimates and interface descriptions. To validate our design, we simulate an uncoded transmission over a downlink multiuser channel using the LabVIEW software, where the SLP IP core is implemented as a clock-driven logic (CDL) unit. Our simulation results show that a throughput of 100 Mega symbols per second per user can be achieved via the proposed SLP design. We further use the MATLAB software to produce numerical results for the conventional zero-forcing (ZF) and the optimal SLP techniques as benchmarks for comparison. Thereby, it is shown that the proposed FPGA implementation of SLP offers an improvement of up to 50 percent in power efficiency compared to the ZF precoding. Remarkably, it enjoys the same per-symbol complexity order as that of the ZF technique. We also evaluate the loss of the real-time SLP design, introduced by the algebraic approximations and arithmetic inaccuracies, with respect to the optimal scheme.
Research center :
Interdisciplinary Centre for Security, Reliability and Trust (SnT) > SIGCOM
Disciplines :
Electrical & electronics engineering
Author, co-author :
Haqiqatnejad, Alireza ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom
Krivochiza, Jevgenij  ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom
Merlano Duncan, Juan Carlos ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom
Chatzinotas, Symeon  ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom
Ottersten, Björn ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT)
External co-authors :
no
Language :
English
Title :
Design Optimization for Low-Complexity FPGA Implementation of Symbol-Level Multiuser Precoding
Publication date :
16 February 2021
Journal title :
IEEE Access
ISSN :
2169-3536
Publisher :
IEEE, United States
Volume :
9
Pages :
30698-30711
Peer reviewed :
Peer Reviewed verified by ORBi
Focus Area :
Security, Reliability and Trust
FnR Project :
FNR11332341 - Enhanced Signal Space Optimization For Satellite Communication Systems, 2016 (01/02/2017-31/01/2020) - Farbod Kayhan
Funders :
FNR - Fonds National de la Recherche [LU]
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