Reference : FPGA Design and Implementation of a Real-time FM/PM Pseudo Random Waveform Generation...
Scientific congresses, symposiums and conference proceedings : Paper published in a book
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/10993/46003
FPGA Design and Implementation of a Real-time FM/PM Pseudo Random Waveform Generation for Noise Radars
English
Tedgue Beltrao, Gabriel mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > SigCom >]
Alisson, Barreto [Brazilian Army Technology Center - CTEx > Radar Division]
Leandro, Pralon [Brazilian Army Technology Center - CTEx > Radar Division]
Bruno, Pompeo [Brazilian Army Technology Center > Radar Division]
Mariana, Pralon [Brazilian Army Technology Center - CTEx > Radar Division]
2020
Proceedings of the 2020 IEEE Radar Conference (RadarConf20), Florence, Italy, 2020
Yes
2020 IEEE Radar Conference (RadarConf20)
from 21-09-2020 to 25-09-2020
[en] Noise Radar ; pseudo-random waveform ; frequency modulation ; FPGA
[en] Noise Radar technology is the general term used to describe radar systems that employ realizations of a given stochastic process as transmit waveforms. With the advances made in hardware as well as the rise of the software defined noise radar concept, waveform design emerges as an important research area related to such systems. Several optimization algorithms have been proposed to generate pseudo-random waveforms with specific desired features, specially with respect to sidelobes. Nevertheless, not only modifying random waveforms may
compromise their LPI performance, but also the implementation of such algorithms in real time applications may not be feasible. Within this context, this paper analyzes varied design architectures for FM/PM pseudo-noise waveform generation, considering a real-time application. The proposed architectures are verified in a co-simulation environment using the Xilinx System Generator tool and implemented on reconfigurable hardware, i.e., a Xilinx Field Programmable Gate Array (FPGA) is taken into consideration. Timing, resource consumption, and the trade-offs related to hardware area and performance are then investigated.
http://hdl.handle.net/10993/46003

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