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Minimizing CPU Time Shortage Risks in Integrated Embedded Software
Nejati, Shiva; Adedjouma, Morayo; Briand, Lionel et al.
2013In 28th IEEE/ACM International Conference on Automated Software Engineering
Peer reviewed
 

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Research center :
Interdisciplinary Centre for Security, Reliability and Trust (SnT) > Software Verification and Validation Lab (SVV Lab)
Disciplines :
Computer science
Author, co-author :
Nejati, Shiva ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT)
Adedjouma, Morayo ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT)
Briand, Lionel ;  University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) ; University of Luxembourg > Faculty of Science, Technology and Communication (FSTC) > Computer Science and Communications Research Unit (CSC)
Hellebaut, Jonathan;  Delphi Automotive Systems, Luxembourg
Begey, Julien;  Delphi Automotive Systems, Luxembourg
Clement, Yves;  Delphi Automotive Systems, Luxembourg
External co-authors :
no
Language :
English
Title :
Minimizing CPU Time Shortage Risks in Integrated Embedded Software
Publication date :
2013
Event name :
28th IEEE/ACM International Conference on Automated Software Engineering
Event place :
Silicon Valley, United States
Event date :
November 11 - 15, 2013
By request :
Yes
Audience :
International
Main work title :
28th IEEE/ACM International Conference on Automated Software Engineering
Peer reviewed :
Peer reviewed
Available on ORBilu :
since 26 July 2013

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