Reference : Uncertainty-aware Specification and Analysis for Hardware-in-the-Loop Testing of Cybe...
Scientific journals : Article
Engineering, computing & technology : Computer science
Security, Reliability and Trust
http://hdl.handle.net/10993/44144
Uncertainty-aware Specification and Analysis for Hardware-in-the-Loop Testing of Cyber Physical Systems
English
Shin, Seung Yeob mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Chaouch, Karim [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Nejati, Shiva mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Sabetzadeh, Mehrdad mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Briand, Lionel mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Zimmer, Frank []
2020
Journal of Systems and Software
Yes
International
[en] Test Case Specification and Analysis ; Cyber Physical Systems ; UML Profile ; Simulation ; Model Checking ; Machine Learning
[en] Hardware-in-the-loop (HiL) testing is important for developing cyber physical systems (CPS). HiL test cases manipulate hardware, are time-consuming and their behaviors are impacted by the uncertainties in the CPS environment. To mitigate the risks associated with HiL testing, engineers have to ensure that (1) test cases are well-behaved, e.g., they do not damage hardware, and (2) test cases can execute within a time budget. Leveraging the UML profile mechanism, we develop a domain-specific language, HITECS, for HiL test case specification. Using HITECS, we provide uncertainty-aware analysis methods to check the well-behavedness of HiL test cases. In addition, we provide a method to estimate the execution times of HiL test cases before the actual HiL testing. We apply HITECS to an industrial case study from the satellite domain. Our results show that: (1) HITECS helps engineers define more effective assertions to check HiL test cases, compared to the assertions defined without any systematic guidance; (2) HITECS verifies in practical time that HiL test cases are well-behaved; (3) HITECS is able to resolve uncertain parameters of HiL test cases by synthesizing conditions under which test cases are guaranteed to be well-behaved; and (4) HITECS accurately estimates HiL test case execution times.
Interdisciplinary Centre for Security, Reliability and Trust (SnT) > Software Verification and Validation Lab (SVV Lab)
Researchers ; Professionals ; Students ; General public ; Others
http://hdl.handle.net/10993/44144
10.1016/j.jss.2020.110813
H2020 ; 694277 - TUNE - Testing the Untestable: Model Testing of Complex Software-Intensive Systems
FnR ; FNR11270448 > Lionel Briand > MOSIS > Model-Based Simulation of Integrated Software Systems > 01/01/2017 > 31/12/2019 > 2016

File(s) associated to this reference

Fulltext file(s):

FileCommentaryVersionSizeAccess
Open access
journal.pdfAuthor postprint2.53 MBView/Open

Bookmark and Share SFX Query

All documents in ORBilu are protected by a user license.