Reference : Lightweight Post-quantum Key Encapsulation for 8-bit AVR Microcontrollers
Scientific congresses, symposiums and conference proceedings : Paper published in a book
Engineering, computing & technology : Computer science
Security, Reliability and Trust
http://hdl.handle.net/10993/48811
Lightweight Post-quantum Key Encapsulation for 8-bit AVR Microcontrollers
English
Cheng, Hao mailto [University of Luxembourg > Faculty of Science, Technology and Medicine (FSTM) > APSIA >]
Groszschädl, Johann mailto [University of Luxembourg > Faculty of Science, Technology and Medicine (FSTM) > Department of Computer Science (DCS) >]
Roenne, Peter mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > APSIA >]
Ryan, Peter Y A mailto [University of Luxembourg > Faculty of Science, Technology and Medicine (FSTM) > Department of Computer Science (DCS) >]
Nov-2020
Smart Card Research and Advanced Applications, 19th International Conference, CARDIS 2020, Virtual Event, November 18–19, 2020, Revised Selected Papers
Liardet, Pierre-Yvan
Mentens, Nele
Springer Verlag
Lecture Notes in Computer Science, volume 12609
18-33
Yes
International
978-3-030-68486-0
19th Smart Card Research and Advanced Application Conference (CARDIS 2020)
2020-11-18 to 2020-11-19
Lübeck
Germany
[en] Post-quantum cryptography ; Key encapsulation mechanism ; AVR architecture ; Efficient implementation ; Low RAM footprint
[en] Recent progress in quantum computing has increased interest in the question of how well the existing proposals for post-quantum cryptosystems are suited to replace RSA and ECC. While some aspects of this question have already been researched in detail (e.g. the relative computational cost of pre- and post-quantum algorithms), very little is known about the RAM footprint of the proposals and what execution time they can reach when low memory consumption rather than speed is the main optimization goal. This question is particularly important in the context of the Internet of Things (IoT) since many IoT devices are extremely constrained and possess only a few kB of RAM. We aim to contribute to answering this question by exploring the software design space of the lattice-based key-encapsulation scheme ThreeBears on an 8-bit AVR microcontroller. More concretely, we provide new techniques for the optimization of the ring arithmetic of ThreeBears (which is, in essence, a 3120-bit modular multiplication) to achieve either high speed or low RAM footprint, and we analyze in detail the trade-offs between these two metrics. A low-memory implementation of BabyBear that is secure against Chosen Plaintext Attacks (CPA) needs just about 1.7 kB RAM, which is significantly below the RAM footprint of other lattice-based cryptosystems reported in the literature. Yet, the encapsulation time of this RAM-optimized BabyBear version is below 12.5 million cycles, which is less than the execution time of scalar multiplication on Curve25519. The decapsulation is more than four times faster and takes roughly 3.4 million cycles on an ATmega1284 microcontroller.
Interdisciplinary Centre for Security, Reliability and Trust (SnT) > Applied Security and Information Assurance Group (APSIA)
European Commission - EC
http://hdl.handle.net/10993/48811
10.1007/978-3-030-68487-7_2
https://link.springer.com/chapter/10.1007/978-3-030-68487-7_2
H2020 ; 779391 - FutureTPM - Future Proofing the Connected World: A Quantum-Resistant Trusted Platform Module

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