Reference : PRACE Best Practice Guide 2021: Modern Accelerators
Reports : Expert report
Engineering, computing & technology : Computer science
Computational Sciences
PRACE Best Practice Guide 2021: Modern Accelerators
Bispo, João [University of Porto, Portugal]
Barbosa, Jorge G. [University of Porto, Portugal]
Filipe Silva, Pedro [University of Porto, Portugal]
Morales, Cristian [BCS, Spain]
Myllykoski, Mirko [HPC2N, Sweden]
Ojeda-May, Pedro [HPC2N, Sweden]
Bialczak, Milosz [WCSS, Poland]
Uchronski, Mariusz [WCSS, Poland]
Wlodarczyk, Adam [WCSS, Poland]
Wauligmann, Peter [HLRS, Germany]
Krishnasamy, Ezhilmathi mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > PCOG >]
Varrette, Sébastien mailto [University of Luxembourg > Faculty of Science, Technology and Medicine (FSTM) > Department of Computer Science (DCS) >]
Lührs, Sebastian [JSC, Germany]
PRACE aisbl
PRACE Best Practice Guides
[en] HPC ; GPU
[en] Hardware accelerators are special types of elements designed for boosting the performance of certain application
regions requiring large amounts of numerical computations. Several factors contributed to broadening the use and
furthering the adoption of these technologies in High-Performance Computing (HPC). One of such is the offered
greater computational throughput as compared to stand-alone Central Processing Units (CPUs), which is driven
by the highly parallel architectural design of accelerators. This is particularly important in the current era of ever-increasing computational demands featuring high reuse rates of compute-intensive operational patterns. Another
contributing factor is that these specialized chips are also capable of delivering much higher compute performance
as compared to CPUs under the same power budget, making these technologies even more appealing for system
vendors and users. All these led HPC manufacturers and integrators to unleash further the potential of hardware
accelerators for delivering the required compute performance more efficiently. In fact, this is one of the main
reasons that the current Top500 list [1] continues to be enriched with various accelerated systems.
The next generation of HPC systems will also see a considerable amount of accelerator technology used. As a
matter of fact, two out of the three European High-Performance Computing Joint Undertaking (EuroHPC JU) [2]
pre-exascale HPC sites have already announced that their supercomputers will be equipped with large amount
of Graphics Processing Units (GPUs). Thus, in order to achieve a competitive application performance and to
be able to use the underlying hardware infrastructure efficiently, HPC application developers should be familiar
with various challenges associated with using and orchestrating vast amounts of accelerator devices while being
acquainted with the available ecosystem of the supporting tools.
This Best Practice Guide (BPG) extends the previously developed series of BPGs [3] by providing an update on
new accelerator technologies to further support the European HPC user community in achieving outstanding performance records of their large-scale parallel applications. This guide follows the style of the previously published
guide on "Modern Processors" [4], by providing a hybrid approach of a field guide and a textbook. The aim of this
BPG is not to replace any of the available in depth textbooks and/or documentations of certain tools, but rather to
provide a set of best practices that build upon the available literature and the expertise of authors involved to further ease the process of application porting and performance optimisation. This guide showcases the usability and
possibilities of further application tuning given a specific accelerator technology, and does not provide any direct
comparisons of different accelerator technologies involved. The guide provides a generic overview on various accelerators and their accompanying programming models/environments and thus should be viewed as complementary to the existing in-depth BPGs provided by hardware vendors that are typically specific to their own product.
University of Luxembourg: High Performance Computing - ULHPC
H2020 ; 823767 - PRACE-6IP - PRACE 6th Implementation Phase Project

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