A probabilistic and timed verification approach of SysML state machine diagram

Reference : A probabilistic and timed verification approach of SysML state machine diagram


	Document type :	Scientific congresses, symposiums and conference proceedings : Paper published in a book
	Discipline(s) :	Engineering, computing & technology : Computer science
	To cite this reference:	http://hdl.handle.net/10993/24851

Title :	A probabilistic and timed verification approach of SysML state machine diagram
Language :	English
Author, co-author :	Baouya, Abdelhakim [> >]
	Bennouar, Djamal [> >]
	Mohamed, Otmane Ait [> >]
	Ouchani, Samir [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) >]
Publication date :	2015
Main document title :	A probabilistic and timed verification approach of SysML state machine diagram
Peer reviewed :	Yes
Event name :	12th International Symposium on Programming and Systems (ISPS), 2015
Event date :	2015
Event organizer :	IEEE
Permalink :	http://hdl.handle.net/10993/24851
Commentary :	1--9

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	File	Commentary	Version	Size	Access
Open access	ISPS2015_submission_24.pdf		Author preprint	2.78 MB	View/Open

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