| A probabilistic and timed verification approach of SysML state machine diagram |
| English |
| Baouya, Abdelhakim [> >] |
| Bennouar, Djamal [> >] |
| Mohamed, Otmane Ait [> >] |
| Ouchani, Samir [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) >] |
| 2015 |
| A probabilistic and timed verification approach of SysML state machine diagram |
| Yes |
| 12th International Symposium on Programming and Systems (ISPS), 2015 |
| 2015 |
| IEEE |
| http://hdl.handle.net/10993/24851 |
| 1--9 |