FPGA Acceleration for Computationally Efficient Symbol-Level Precoding in Multi-User Multi-Antenna Communication Systems

In this paper, we demonstrate an FPGA accelerated design of the computationally efficient Symbol-Level Precoding (SLP) for high-throughput communication systems. The SLP technique recalculates optimal beam-forming vectors by solving a non-negative least squares (NNLS) problem per every set of transmitted symbols. It exploits the advantages of constructive inter-user interference to minimize the total transmitted power and increase service availability. The benefits of using SLP come with a substantially increased computational load at a gateway. The FPGA design enables the SLP technique to perform in realtime operation mode and provide a high symbol throughput for multiple receive terminals. We define the SLP technique in a closed-form algorithmic expression and translate it to Hardware Description Language (HDL) and build an optimized HDL core for an FPGA. We evaluate the FPGA resource occupation, which is required for high throughput multiple-input-multiple-output (MIMO) systems with sizeable dimensions. We describe the algorithmic code, the I/O ports mapping and the functional behavior of the HDL core. We deploy the IP core to an actual FPGA unit and benchmark the energy efficiency performance of SLP. The synthetic tests demonstrate a fair energy efficiency improvement of the proposed closed-form algorithm, also compared to the best results obtained through MATLAB numerical simulations.