Reference : Elliptic Curve Cryptography with Efficiently Computable Endomorphisms and Its Hardwar...

	Document type :	Scientific journals : Article
	Discipline(s) :	Engineering, computing & technology : Computer science
	Focus Areas :	Security, Reliability and Trust
	To cite this reference:	http://hdl.handle.net/10993/37495

Title :	Elliptic Curve Cryptography with Efficiently Computable Endomorphisms and Its Hardware Implementations for the Internet of Things
Language :	English
Author, co-author :	Liu, Zhe [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > Computer Science and Communications Research Unit (CSC) >]
	Groszschädl, Johann [University of Luxembourg > Faculty of Science, Technology and Communication (FSTC) > Computer Science and Communications Research Unit (CSC) >]
	Hu, Zhi [Central South University > School of Mathematics and Statistics]
	Järvinen, Kimmo [Katholieke Universiteit Leuven > Department of Electrical Engineering (ESAT)]
	Wang, Husen [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
	Verbauwhede, Ingrid [Katholieke Universiteit Leuven > Department of Electrical Engineering (ESAT)]
Publication date :	May-2017
Journal title :	IEEE Transactions on Computers
Publisher :	Institute of Electrical and Electronics Engineers
Volume :	66
Issue/season :	5
Pages :	773-785
Peer reviewed :	Yes (verified by ORBilu)
ISSN :	0018-9340
e-ISSN :	1557-9956
City :	Los Alamitos
Country :	CA
Keywords :	[en] Cryptographic Hardware ; Elliptic Curve Cryptography ; Twisted Edwards Curves ; Efficiently-Computable Endomorphism ; Multiple-Precision Modular Arithmetic ; ASIC Implementation
Abstract :	[en] Verification of an ECDSA signature requires a double scalar multiplication on an elliptic curve. In this work, we study the computation of this operation on a twisted Edwards curve with an efficiently computable endomorphism, which allows reducing the number of point doublings by approximately 50 percent compared to a conventional implementation. In particular, we focus on a curve defined over the 207-bit prime field Fp with p = 2^207 - 5131. We develop several optimizations to the operation and we describe two hardware architectures for computing the operation. The first architecture is a small processor implemented in 0.13 μm CMOS ASIC and is useful in resource-constrained devices for the Internet of Things (IoT) applications. The second architecture is designed for fast signature verifications by using FPGA acceleration and can be used in the server-side of these applications. Our designs offer various trade-offs and optimizations between performance and resource requirements and they are valuable for IoT applications.
Permalink :	http://hdl.handle.net/10993/37495
DOI :	10.1109/TC.2016.2623609
Other URL :	http://ieeexplore.ieee.org/document/7727929

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