![]() Colombara, Diego ![]() in Thin Solid Films (2011), 519(21), 74387443 Due to the availability and low cost of the elements, the ternary Cu–Sb–S and Cu–Sb–Se semiconductor systems are being studied as sustainable alternative absorber materials to replace CuIn(Ga)(S,Se)2 in ... [more ▼] Due to the availability and low cost of the elements, the ternary Cu–Sb–S and Cu–Sb–Se semiconductor systems are being studied as sustainable alternative absorber materials to replace CuIn(Ga)(S,Se)2 in thin film photovoltaic applications. Simple evaporation of the metal precursors followed by annealing in a chalcogen environment has been employed in order to test the feasibility of converting stacked metallic layers into the desired compounds. Other samples have been produced from aqueous solutions by electrochemical methods that may be suitable for scale-up. It was found that the minimum temperature required for the complete conversion of the precursors into the ternary chalcogen is 350 °C, while binary phase separation occurs at lower temperatures. The new materials have been characterised by structural, electrical and photoelectrochemical techniques in order to establish their potential as absorber layer materials for photovoltaic applications. The photoactive films consisting of CuSbS2 and CuSbSe2 exhibit band-gap energies of ~ 1.5 eV and ~ 1.2 eV respectively, fulfilling the Shockley–Queisser requirements for the efficient harvesting of the solar spectrum. [less ▲] Detailed reference viewed: 133 (4 UL)![]() ; ; et al in Thin Solid Films (2011), 519 Detailed reference viewed: 93 (0 UL)![]() ; ; et al in Thin Solid Films (2011), 519 Detailed reference viewed: 113 (2 UL)![]() Steichen, Marc ![]() ![]() ![]() in Thin Solid Films (2011), 519 Detailed reference viewed: 180 (3 UL)![]() Larsen, Jes K. ![]() ![]() ![]() in Thin Solid Films (2011), 519 Detailed reference viewed: 168 (4 UL)![]() ; ; et al in Thin Solid Films (2011), 519 Detailed reference viewed: 154 (3 UL)![]() ; Dale, Phillip ![]() in Thin Solid Films (2009), 517(7), 2481-2484 An electrodeposition-annealing route to films of the promising p-type absorber material Cu2ZnSnS4 (CZTS) using layered metal precursors is studied. The dependence of device performance on composition is ... [more ▼] An electrodeposition-annealing route to films of the promising p-type absorber material Cu2ZnSnS4 (CZTS) using layered metal precursors is studied. The dependence of device performance on composition is investigated, and it is shown that a considerable Cu-deficiency is desirable to produce effective material, as measured by photoelectrochemical measurements employing the Eu3+/2+ redox couple. The differing effects of using elemental sulphur and H2S as sulphur sources during annealing are also studied, and it is demonstrated that H2S annealing results in films with improved crystallinity. [less ▲] Detailed reference viewed: 110 (1 UL)![]() Marso, Michel ![]() in Thin Solid Films (2001), 382(2001), 218-221 Porous silicon superlattices have been used to manufacture laterally displaced dielectric filters with different optical properties on one substrate. Two different fabrication processes for two-colour ... [more ▼] Porous silicon superlattices have been used to manufacture laterally displaced dielectric filters with different optical properties on one substrate. Two different fabrication processes for two-colour microfilter arrays are presented. Both methods overcome the problem of non-uniform optical properties of the well-known procedure where two filter stacks are grown one upon another, with subsequent partial removal of the upper filter by reactive ion etching. The novel methods give uniform optical properties of the two filter areas, profiting from the main property of the formation process of porous silicon: the formation of porous silicon occurs only at the porous silicon substrate interface. [less ▲] Detailed reference viewed: 130 (0 UL)![]() ; ; et al in Thin Solid Films (1998), 336(1998), 306-308 Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving ... [more ▼] Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving short channel lengths and high integration densities while still using optical lithography to define lateral dimensions. Compared to other vertical concepts, this layout has reduced gate to source/drain overlap capacitances which is necessary for high speed applications. The use of SEG instead of blanket epitaxy avoids the deterioration of the Si/SiO2 interface due to reactive ion etching (RIE) and reduces punch-through due to facet growth. First non-optimized p-channel MOSFETs with a 12-nm gate oxide show a transconductance of 90 mS/mm. The cut-off frequencies of this device turned out to be f T = 2.3 GHz and f max = 1.1 GHz. [less ▲] Detailed reference viewed: 101 (2 UL)![]() ; Marso, Michel ![]() in Thin Solid Films (1997), 297(1997), 241-244 Detailed reference viewed: 90 (0 UL) |
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