Performance of unpassivated AlGaN/GaN/SiC HEMTs after short-term electrical bias stress

in Solid-State Electronics (2004), 48((2004)), 1825-1828

Performance of unpassivated MOVPE grown AlGaN/GaN/SiC HEMTs under short-term electrical bias stress isreported. Insignificant degradation in DC and RF behaviour of prepared devices after 16 h stress at VD ... [more ▼]

Performance of unpassivated MOVPE grown AlGaN/GaN/SiC HEMTs under short-term electrical bias stress isreported. Insignificant degradation in DC and RF behaviour of prepared devices after 16 h stress at VD ¼ 21 V and VG ¼ 2:5 V is observed. This can be demonstrated by a maximum drain current of 1.03 and 1.01 A/mm and a peak extrinsic transconductance of 233 and 225 mS/mm before and after bias stress, respectively. Consecutive drain voltage sweeps indicates on low current collapse in samples investigated. The RF characteristics show a decrease of the fmax-tof T ratio from 2.23 to 2.15 and the saturated output power density measured at 2 GHz from 3.60 to 3.53 W/mm after the devices were stressed. This result indicates that reliable AlGaN/GaN/SiC HEMTs without passivation can be prepared. However, additional studies are needed to understand if the material structure and/or the device processing is responsible for low current collapse and RF dispersion in these devices. [less ▲]

Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth

in Solid-State Electronics (1999), 43(1999), 529-535

A novel vertical MOSFET concept using selective epitaxial growth by low pressure chemical vapor deposition is proposed and the ®rst p-channel device characteristics measured are described. In contrast to ... [more ▼]

A novel vertical MOSFET concept using selective epitaxial growth by low pressure chemical vapor deposition is proposed and the ®rst p-channel device characteristics measured are described. In contrast to other MOS technologies, the gate oxide is deposited before epitaxy, and therefore it exists before the channel region is grown. Compared to planar layouts, the vertical layout increases the packing density without the use of advanced lithography; the extent of the increase depends on application. Compared to other vertical transistors, this concept reduces overlap capacitance and o ers the possibility of three-dimensional integration. Vertical p channel MOSFETs with a channel length LG down to 130 nm and a gate oxide thickness dox down to 12 nm have been fabricated and yield a transconductance of 100 mS mm-1. [less ▲]

Electrical Behaviour of the InP/InGaAs Based MSM-2DEG Diode

in Solid-State Electronics (1997), 41(1997), 25-31