Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors,

in Physica E: Low-Dimensional Systems and Nanostructures (2003), 19(2003), 18-22

In this work, we present an approach towards improving a vertical eld-e ect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does ... [more ▼]

In this work, we present an approach towards improving a vertical eld-e ect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant di ffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed. [less ▲]

Vertical Double-Gate MOSFET Based on Epitaxial Growth

in Proceedings of the 31st European Solid State Devices Research Conference, Nürnberg, Germany (2001)

Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth

in Solid-State Electronics (1999), 43(1999), 529-535

A novel vertical MOSFET concept using selective epitaxial growth by low pressure chemical vapor deposition is proposed and the ®rst p-channel device characteristics measured are described. In contrast to ... [more ▼]

A novel vertical MOSFET concept using selective epitaxial growth by low pressure chemical vapor deposition is proposed and the ®rst p-channel device characteristics measured are described. In contrast to other MOS technologies, the gate oxide is deposited before epitaxy, and therefore it exists before the channel region is grown. Compared to planar layouts, the vertical layout increases the packing density without the use of advanced lithography; the extent of the increase depends on application. Compared to other vertical transistors, this concept reduces overlap capacitance and o ers the possibility of three-dimensional integration. Vertical p channel MOSFETs with a channel length LG down to 130 nm and a gate oxide thickness dox down to 12 nm have been fabricated and yield a transconductance of 100 mS mm-1. [less ▲]

Selectively Grown Vertical Si MOS Transistor with Reduced Overlap Capacitances

in Thin Solid Films (1998), 336(1998), 306-308

Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving ... [more ▼]

Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving short channel lengths and high integration densities while still using optical lithography to define lateral dimensions. Compared to other vertical concepts, this layout has reduced gate to source/drain overlap capacitances which is necessary for high speed applications. The use of SEG instead of blanket epitaxy avoids the deterioration of the Si/SiO2 interface due to reactive ion etching (RIE) and reduces punch-through due to facet growth. First non-optimized p-channel MOSFETs with a 12-nm gate oxide show a transconductance of 90 mS/mm. The cut-off frequencies of this device turned out to be f T = 2.3 GHz and f max = 1.1 GHz. [less ▲]