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See detailExploiting Transistor-Level Reconfiguration to Optimize Combinational Circu
Raitza, Michael; Kumar, Akash; Volp, Marcus UL et al

Scientific Conference (2017, March)

Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free ... [more ▼]

Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free technology. However, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so far. In this paper, we present first steps to a new compact and efficient design of combinational circuits by employing transistor-level reconfiguration. We contribute new basic gates realized with silicon nanowires, such as 2/3-XOR and MUX gates. Exemplifying our approach with 4-bit, 8-bit and 16-bit conditional carry adders, we were able to reduce the number of transistors to almost one half. With our current case study we show that SiNW technology can reduce the required chip area by 16 %, despite larger size of the individual transistor, and improve circuit speed by 26 %. [less ▲]

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See detailFormally Verified Differential Dynamic Logic
Bohrer, Brandon; Rahli, Vincent UL; Vukotic, Ivana UL et al

in CPP 2017 (2017)

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See detailAvoiding Leakage and Synchronization Attacks through Enclave-Side Preemption Control
Volp, Marcus UL; Lackorzynski, Adam; Decouchant, Jérémie UL et al

Scientific Conference (2016, December 12)

Intel SGX is the latest processor architecture promising secure code execution despite large, complex and hence potentially vulnerable legacy operating systems (OSs). However, two recent works identified ... [more ▼]

Intel SGX is the latest processor architecture promising secure code execution despite large, complex and hence potentially vulnerable legacy operating systems (OSs). However, two recent works identified vulnerabilities that allow an untrusted management OS to extract secret information from Intel SGX's enclaves, and to violate their integrity by exploiting concurrency bugs. In this work, we re-investigate delayed preemption (DP) in the context of Intel SGX. DP is a mechanism originally proposed for L4-family microkernels as disable-interrupt replacement. Recapitulating earlier results on language-based information-flow security, we illustrate the construction of leakage-free code for enclaves. However, as long as adversaries have fine-grained control over preemption timing, these solutions are impractical from a performance/complexity perspective. To overcome this, we resort to delayed preemption, and sketch a software implementation for hypervisors providing enclaves as well as a hardware extension for systems like SGX. Finally, we illustrate how static analyses for SGX may be extended to check confidentiality of preemption-delaying programs. [less ▲]

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See detailThe Orchestration Stack: The Impossible Task of Designing Software for Unknown Future Post-CMOS Hardware
Volp, Marcus UL; Klüppelholz, Sascha; Castrillon, Jeronimo et al

Scientific Conference (2016, November 14)

Future systems based on post-CMOS technologies will be wildly heterogeneous, with properties largely unknown today. This paper presents our design of a new hardware/software stack to address the challenge ... [more ▼]

Future systems based on post-CMOS technologies will be wildly heterogeneous, with properties largely unknown today. This paper presents our design of a new hardware/software stack to address the challenge of preparing software development for such systems. It combines well-understood technologies from different areas, e.g., network-on-chips, capability operating systems, flexible programming models and model checking. We describe our approach and provide details on key technologies. [less ▲]

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See detailTowards Safe and Secure Autonomous and Cooperative Vehicle Ecosystems
Caldeira Lima, Antonio UL; Rocha, Francisco UL; Volp, Marcus UL et al

in Proceedings of the Second ACM Workshop on Cyber-Physical Systems Security and PrivaCy (2016, October)

Semi-autonomous driver assists are already widely deployed and fully autonomous cars are progressively leaving the realm of laboratories. This evolution coexists with a progressive connectivity and ... [more ▼]

Semi-autonomous driver assists are already widely deployed and fully autonomous cars are progressively leaving the realm of laboratories. This evolution coexists with a progressive connectivity and cooperation, creating important safety and security challenges, the latter ranging from casual hackers to highly-skilled attackers, requiring a holistic analysis, under the perspective of fully-fledged ecosystems of autonomous and cooperative vehicles. This position paper attempts at contributing to a better understanding of the global threat plane and the specific threat vectors designers should be at- tentive to. We survey paradigms and mechanisms that may be used to overcome or at least mitigate the potential risks that may arise through the several threat vectors analyzed. [less ▲]

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See detailM3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores
Asmussen, Nils; Volp, Marcus UL; Nöthen, Benedikt et al

in Architectural Support for Programming Languages and Operating Systems (ASPLOS) (2016, April)

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See detailTowards Dependable CPS Infrastructures: Architectural and Operating-System Challenges
Volp, Marcus UL; Asmussen, Nils; Härtig, Hermann et al

Scientific Conference (2015)

Detailed reference viewed: 75 (4 UL)