Reference : FPGA Acceleration for Computationally Efficient Symbol-Level Precoding in Multi-User ...
Scientific journals : Article
Engineering, computing & technology : Computer science
Computational Sciences
http://hdl.handle.net/10993/38797
FPGA Acceleration for Computationally Efficient Symbol-Level Precoding in Multi-User Multi-Antenna Communication Systems
English
Krivochiza, Jevgenij mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Merlano Duncan, Juan Carlos mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Andrenacci, Stefano mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Chatzinotas, Symeon mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Ottersten, Björn mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
2019
IEEE Access
Yes
International
2169-3536
[en] Convex programming ; Field programmable gate arrays ; Hardware resources ; Multicast communication ; MIMO ; Optimization ; Precoding ; Power minimization ; Interference ; Wireless channels
[en] In this paper, we demonstrate an FPGA accelerated design of the computationally efficient Symbol-Level Precoding (SLP) for high-throughput communication systems. The SLP technique recalculates optimal beam-forming vectors by solving a non-negative least squares (NNLS) problem per every set of transmitted symbols. It exploits the advantages of constructive inter-user interference to minimize the total transmitted power and increase service availability. The benefits of using SLP come with a substantially increased computational load at a gateway. The FPGA design enables the SLP technique to perform in realtime operation mode and provide a high symbol throughput for multiple receive terminals. We define the SLP technique in a closed-form algorithmic expression and translate it to Hardware Description Language (HDL) and build an optimized HDL core for an FPGA. We evaluate the FPGA resource occupation, which is required for high throughput multiple-input-multiple-output (MIMO) systems with sizeable dimensions. We describe the algorithmic code, the I/O ports mapping and the functional behavior of the HDL core. We deploy the IP core to an actual FPGA unit and benchmark the energy efficiency performance of SLP. The synthetic tests demonstrate a fair energy efficiency improvement of the proposed closed-form algorithm, also compared to the best results obtained through MATLAB numerical simulations.
Interdisciplinary Centre for Security, Reliability and Trust (SnT) > SIGCOM
Fonds National de la Recherche - FnR
Researchers ; Professionals ; Students ; General public
http://hdl.handle.net/10993/38797
10.1109/ACCESS.2019.2894181
https://doi.org/10.1109/ACCESS.2019.2894181
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FnR ; FNR11481283 > Jevgenij Krivochiza > > End-to-end Signal Processing Algorithms for Precoded Satellite Communications > 01/03/2017 > 28/02/2021 > 2016

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