Reference : Facing the Safety-Security Gap in RTES: the Challenge of Timeliness
Scientific congresses, symposiums and conference proceedings : Unpublished conference
Engineering, computing & technology : Computer science
http://hdl.handle.net/10993/34057
Facing the Safety-Security Gap in RTES: the Challenge of Timeliness
English
Volp, Marcus mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Kozhaya, David mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Verissimo, Paulo mailto [University of Luxembourg > Interdisciplinary Centre for Security, Reliability and Trust (SNT) > >]
Dec-2017
8
Yes
2nd Workshop on Security and Dependability of Critical Embedded Real-Time Systems (CERTS 2017) co-located with RTSS 2017
05-08 December 2017
[en] Safety-critical real-time systems, including real-time
cyber-physical and industrial control systems, need not be solely
correct but also timely. Untimely (stale) results may have severe
consequences that could render the control system’s behaviour
hazardous to the physical world. To ensure predictability and
timeliness, developers follow a rigorous process, which essentially
ensures real-time properties a priori, in all but the most unlikely
combinations of circumstances. However, we have seen the
complexity of both real-time applications, and the environments
they run on, increase. If this is matched with the also increasing
sophistication of attacks mounted to RTES systems, the case for
ensuring both safety and security through aprioristic predictability
loses traction, and presents an opportunity, which we take
in this paper, for discussing current practices of critical realtime
system design. To this end, with a slant on low-level task
scheduling, we first investigate the challenges and opportunities
for anticipating successful attacks on real-time systems. Then,
we propose ways for adapting traditional fault- and intrusiontolerant
mechanisms to tolerate such hazards. We found that
tasks which typically execute as analyzed under accidental faults,
may exhibit fundamentally different behavior when compromised
by malicious attacks, even with interference enforcement in place.
Researchers ; Students
http://hdl.handle.net/10993/34057
FnR ; FNR8149128 > Paulo Esteves-Veríssimo > IISD > Strategic Rtnd Program On Information Infrastructure Security And Dependability > 01/01/2015 > 31/12/2019 > 2014

File(s) associated to this reference

Fulltext file(s):

FileCommentaryVersionSizeAccess
Open access
Timeliness-SafeSecGap.pdfAuthor preprint495.2 kBView/Open

Bookmark and Share SFX Query

All documents in ORBilu are protected by a user license.