Reference : Phase-error correction by single-phase phase-locked loops based on transfer delay
Scientific congresses, symposiums and conference proceedings : Paper published in a journal
Engineering, computing & technology : Electrical & electronics engineering
Engineering, computing & technology : Energy
Sustainable Development
http://hdl.handle.net/10993/27344
Phase-error correction by single-phase phase-locked loops based on transfer delay
English
Kobou Ngani, Patrick mailto [University of Luxembourg > Faculty of Science, Technology and Communication (FSTC) > Engineering Research Unit >]
Hadji-Minaglou, Jean-Régis mailto [University of Luxembourg > Faculty of Science, Technology and Communication (FSTC) > Engineering Research Unit >]
Marso, Michel mailto [University of Luxembourg > Faculty of Science, Technology and Communication (FSTC) > Engineering Research Unit >]
De Jaeger, Emmanuel mailto [Université Catholique de Louvain - UCL]
4-Nov-2015
Journal of Electrical & Electronic Systems
ScientificTracks Abstracts
No
Global Summit on Electronics and Electrical Engineering
from 03/11/2015 to 05/11/2015
Omics International
Valencia
Spain
[en] single-phase PLL ; Transfer delay PLL ; phase-angle correction
[en] Comparative studies of different single-phase phase-locked loops (PLL) algorithms have been made. They show that the PLL based on sample delay (dPLL), presents the lowest computational load and is as robust as the three-phase synchronous reference frame PLL dqPLL by input signal amplitude and phase variations. Its weakness appears when the input signal frequency differs from its rated frequency: It depicts a steady error on the calculated signal phase-angle. After a brief review of the dqPLL which constitutes debase structure of the dPLL, the following work will present three methods that improve the phase detection accuracy of dPLL. It is shown that the modifications brought in the original structure do not influence the robustness and stability of the algorithm but reduce the phase angle offset error by input signal frequency variation. This is corroborated by tests including not only the fundamental input voltage disturbance like amplitude, phase and frequency variation but also harmonic voltage distortion.
Fonds National de la Recherche - FnR
Researchers ; Professionals ; Students ; General public
http://hdl.handle.net/10993/27344
10.4172/2332-0796.C1.002
http://www.omicsonline.org/proceedings/phaseerror-correction-by-singlephase-phaselocked-loops-based-on-transfer-delay-39583.html
FnR ; FNR8043977 > Patrick Kobou Ngani > > Distributed Harmonics Compensation for the Power Quality in Smart Grids > 01/03/2014 > 31/01/2017 > 2014

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phase_error_correction_dPLL_KNP.pdfAuthor preprint932.92 kBView/Open

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delayPLL improvement.pdfThe presentation made at the conference1.33 MBView/Open

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