Reference : Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances
Scientific congresses, symposiums and conference proceedings : Paper published in a book
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/10993/20676
Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances
English
Klaes, D. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Moers, J. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Tönnesmann, A. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Grimm, M. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Wickenhäuser, S. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Vescan, L. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Marso, Michel mailto [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Kordoš, P. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
Lüth, H. [Institute of Thin Film and Ion Technology (ISI), Research Centre Jülich, D-52425 Jülich, Germany]
1998
Proceedings of the 28th European Solid State Devices Research Conference, Bordeaux, France
568-571
No
28th European Solid State Devices Research Conference, Bordeaux, France
1998
http://hdl.handle.net/10993/20676

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