Reference : Selectively Grown Vertical Si MOS Transistor with Reduced Overlap Capacitances
Scientific journals : Article
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/10993/20659
Selectively Grown Vertical Si MOS Transistor with Reduced Overlap Capacitances
English
Klaes, D. [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
Moers, J. [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
Tönnesmann, A. [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
Wickenhäuser, S. [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
Vescan, L. [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
Marso, Michel mailto [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
Grabolla, T. [Institute for Semiconductor Physics, Walter-Korsing-Strasse 2, 15230 Frankfurt Oder, Germany]
Grimm, M. [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
Lüth, H. [Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany]
1998
Thin Solid Films
Elsevier Science
336
1998
306-308
Yes (verified by ORBilu)
0040-6090
[en] Low pressure chemical vapour deposition ; Selective epitaxial growth ; MOS transistor ; Miller capacitance
[en] Vertical p-MOS transistors with channel length of 130 nm have been fabricated using selective epitaxial growth (SEG) to define the channel region. The vertical layout offers the advantages of achieving short channel lengths and high integration densities while still using optical lithography to define lateral dimensions. Compared to other vertical concepts, this layout has reduced gate to source/drain overlap capacitances which is necessary for high speed applications. The use of SEG instead of blanket epitaxy avoids the deterioration of the Si/SiO2 interface due to reactive ion etching (RIE) and reduces punch-through due to facet growth. First non-optimized p-channel MOSFETs with a 12-nm gate oxide show a transconductance of 90 mS/mm. The cut-off frequencies of this device turned out to be f T = 2.3 GHz and f max = 1.1 GHz.
http://hdl.handle.net/10993/20659

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