Reference : Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors,
Scientific journals : Article
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/10993/20591
Wet low-temperature gate oxidation for nanoscale vertical field-effect transistors,
English
Goryll, M. [Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany]
Moers, J. [Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany]
Trellenkamp, S. [Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany]
Vescan, L. [Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany]
Marso, Michel mailto [Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany]
Kordos, P. [Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany]
Luth, H. [Institute of Thin Films and Interfaces, Research Centre J ulich, D-52425 J ulich, Germany]
2003
Physica E
Elsevier Science
19
2003
18-22
Yes (verified by ORBilu)
1386-9477
[en] Gate oxide ; Vertical field-e ffect transistor ; Low temperature oxidation
[en] In this work, we present an approach towards improving a vertical eld-e ect transistor based on a narrow mesa that is capable of showing complete channel inversion. Contrary to similar concepts it does not necessarily require the use of an SOI substrate due to the chosen vertical layer sequence. An important issue during process flow is the limited thermal budget in order to preserve the desired channel length. Here a low-temperature wet oxidation process is investigated to prevent dopant di ffusion in early process steps. Results on the thickness homogeneity and electrical properties of this gate oxide will be presented and discussed.
http://hdl.handle.net/10993/20591
10.1016/S1386-9477(03)00287-X

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